1. Field of the Invention
The present invention relates to a semiconductor dynamic random access memory (DRAM), and more particularly to a DRAM whose configuration is such that the stored content of a memory cell is read out after the bit line is precharged with a potential equal or close to 1/2 of the power source potential.
2. Description of the Prior Art
In a DRAM in which a large number of memory cells of a one-transistor-one-capacitor type, each consisting of a switching transistor, of which one source electrode and one drain electrode are connected to a bit line and the gate electrodes are connected to a word line, and a capacitance element (cell capacitance) with one of its electrodes connected to the other source electrode and drain electrode of the switching transistor, are arranged in both row and column directions, the other electrode of each cell capacitance (the opposite cell electrode) is often biased to a potential equal to 1/2 of the power source potential for the purpose of increasing the reliability by easing the voltage stress applied to the memory cells.
In connection with the biasing of the opposite cell electrode to a potential equal to 1/2 (intermediate potential) of the source potential, the bit line is precharged with said intermediate potential before the stored content of a memory cell is read out. When the stored content of the memory cell is read out, the potential of the bit line to which the memory cell belongs becomes slightly higher or lower than the intermediate potential in response to the stored content. A sense amplifier compares the potential of this bit line with the intermediate potential, and amplifies it either to the source potential level or the ground potential level in response to its difference from the intermediate potential. The potential level representing the stored content of the memory cell is thereby established. Since the sense amplifier then only has to amplify the potential of the bit line from around the intermediate potential to the source potential or the ground potential, the read-out speed is faster than in a system in which the precharge potential of the bit line is amplified to a level equal to the source potential. Thus a DRAM of a system in which the opposite cell electrode is biased to an intermediate potential and the bit line is precharged with this intermediate potential is more reliable and permits faster read-out. Therefore, many kinds of DRAM's using this system have been developed (see, for instance, 1985 IEEE International Solid State Circuits Conference DIGEST 0F TECHNICAL PAPERS, pp. 252-253, "A 1 MB CMOS DRAM with Fast Page Static Column Modes").
The sense amplifier in the aforementioned DRAM is provided, for instance, with an N-channel type first transistor of which the drain electrodes are connected to the bit line of the object of read-out (object bit line) and the gate electrodes are connected to another bit line (non-object bit line) than said object bit line; an N-channel type second transistor of which the drain electrodes are connected to said non-object bit line; the gate electrodes are connected to said object bit line and the source electrodes are connected to the source electrode of said first transistor; an N-channel type third transistor of which the drain electrodes are connected to the source electrodes of said first and second transistors, the source electrodes are connected to a ground potential point, and the gate electrodes receive an activation control signal; a P-channel type fourth transistor of which the source electrodes are connected to power source terminals, the drain electrodes are connected to said object bit line and the gate electrodes are connected to said non-object bit line; and a P-channel type fifth transistor of which the source electrodes are connected to said power source terminals, the drain electrodes are connected to said non-object bit line and the gate electrodes are connected to said object bit line.
To the P-type substrate over which the N-channel type first, second and third transistors of this sense amplifier are formed is applied a negative potential generated in a substrate potential generating circuit in order to raise the threshold voltages of these transistors. On this P-type substrate are also formed, with an insulating film in-between, power supply terminals and power supply wiring for supplying power from an external source to circuits including the substrate potential generating circuit. The intermediate potential supplied to the opposite cell electrodes and bit lines are generated by an intermediate potential generating circuit to which power is supplied from an external source.
When the power supply to this DRAM is turned on and the source potential begins to rise, the potential of said substrate is first raised by the parasitic capacitance of the power supply terminals and the power supply wiring, which are directly connected to the power source , with the substrate, because the output of said substrate potential generating circuit has a delay time. As the substrate potential rises, the threshold voltages of the N-channel type first, second and third transistors of the sense amplifier drop, and these transistors achieve continuity. At this time, since the intermediate potential is supplied to the opposite cell electrodes and the bit lines by the intermediate potential generating circuit, a current due to this intermediate potential flows to the ground potential point through the bit lines and the first, second and third transistors. As a result, a leakage current occurs from the channels of these transistors to the substrate, resulting in a further rise in the potential of the substrate and a further increase in current due to the intermediate potential.
In this state, the PNPN junction parts between these N-channel type transistors and P-channel type fourth and fifth transistors become susceptible to a latch-up phenomenon, which would make a current keep flowing to the PNPN junction parts, thereby inviting not only failure of the circuits to function normally but also breakdowns of circuit elements.
Unless a latch-up phenomenon occurs, as the absolute value of the negative substrate potential due to the substrate potential generating circuit increases with the lapse of time, resulting in the biasing of the P-type substrate of the N-channel type transistors of the sense amplifier to a negative potential, the threshold values of these N-channel type transistors return to their normal level, and these transistors are turned off. After that, this DRAM can resume normal operation.
However, if the number of sense amplifiers is increased to expand the memory capacity, there will arise an increase in the current flowing to the N-type transistors of the sense amplifiers due to the rise in substrate potential at the time the power supply is turned on, inviting a corresponding increase in power consumption.